1. Field of the Invention
The present invention relates generally to electrical substrates, and more particularly to multilayer interconnect substrates.
2. Description of the Related Art
Semiconductor chips are continuing to evolve at a phenomenal rate. However, semiconductor chips must be able to communicate with one another economically and reliably to obtain the benefits of these advances. As a result, semiconductor chips have dramatically changed the role of interconnect substrates (also called printed circuit boards and printed wiring boards). The substrate must not only provide signal routing, but also provide circuit signal matching, thermal management, mechanical support, and electrical functionality. For instance, as semiconductor chips contain more customized circuits, semiconductor chip packages contain higher input/output (I/O) counts and reduced contact pitch, and the higher I/O demands require high density interconnect substrates to support the wiring needs of closely spaced devices.
Interconnect substrates have generally kept pace with these demands by using plated through-holes and multilayering to increase circuit density. Plated through-holes connect circuitry on opposite sides of the substrate by means of holes that are drilled through the substrate and then plated with metal to provide conductivity. Multilayering allows separate circuit layers to be laminated together and then connected to each other by plated through-holes. However, these technologies are over 30 years old and have reached their limitations.
Plated through-holes have reached a practical limit of about 8 mils diameter, below which they become prohibitively expensive. In addition, plated through-holes are inefficient because they extend through the entire substrate while usually connecting only two circuit layers. This interferes with routing, and as layer counts increase the situation gets worse. Blind and buried vias have been developed to partially overcome these problems. A blind via is made by drilling partially through a multilayer so that the outer circuit layer can be connected to an inner circuit layer without disturbing the circuit layers below the inner circuit layer. A buried via is made by drilling and plating a two-sided circuit layer and then laminating it into a multilayer so that only two circuit layers that need to be connected have a plated hole and the remaining circuit layers are undisturbed. While blind and buried vias are helpful, they require more process steps and have the limitation of a mechanically drilled hole. As a result, blind and buried vias are interim solutions that do not adequately provide high I/O density surface mounting or facilitate optimum layer-to-layer wiring.
Multilayered substrates have grown from two layers to 40 layers and more. While theoretically it should be possible to increase the layer count without yield penalty, in practice yields fall rapidly as the layer count gets too high.
In view of the various development stages and limitations in currently available multilayer interconnect substrates, there is a need for a multilayer interconnect substrate that is cost-effective, reliable, manufacturable, provides excellent mechanical and electrical performance and has high density circuitry.
An object of the present invention is to provide a convenient, cost-effective method for manufacturing a high density multilayer interconnect substrate.
In accordance with one aspect of the invention, a method of manufacturing a multilayer interconnect substrate includes providing a first interconnect layer that includes a first conductive trace, wherein the first conductive trace includes a first pillar and a first routing line, and the first pillar protrudes vertically from and is electrically connected to the first routing line, providing a second interconnect layer that includes a second conductive trace, wherein the second conductive trace includes a second pillar and a second routing line, and the second pillar protrudes vertically from and is electrically connected to the second routing line, forming an opening in a dielectric layer between the first and second interconnect layers that exposes portions of the first pillar and the second routing line that were previously covered by the dielectric layer, and forming a connection joint in the opening that contacts and electrically connects the first pillar and the second routing line.
Preferably, the first routing line is planar and provides horizontal routing for the first pillar, the second routing line is planar and provides horizontal routing for the second pillar, the first pillar overlaps the second routing line, and the first pillar does not overlap the second pillar. It is also preferred that the opening exposes a distal portion of the first pillar and a sidewall portion of the second routing line but does not expose the first routing line or the second pillar. It is also preferred that the opening is formed by applying a plasma through a metal mask to the dielectric layer.
The connection joint can be formed by electroplating, electroless plating, ball bonding, solder reflowing or conductive adhesive curing.
In a first embodiment, the first pillar and the first routing line are electroplated to one another, and the second pillar and the second routing line are electroplated to one another. This is accomplished by providing a first metal layer with first and second opposing surfaces, electroplating the first routing line on the first surface of the first metal layer, electroplating a first etch mask on the second surface of the first metal layer, etching the first metal layer thereby forming the first pillar from an unetched portion of the first metal layer that contacts the first etch mask and the first routing line and exposing a portion of the first routing line that was previously covered by the first metal layer, removing the first etch mask, providing a second metal layer with first and second opposing surfaces, electroplating the second routing line on the first surface of the second metal layer, electroplating a second etch mask on the second surface of the second metal layer, disposing the dielectric layer between the first pillar and the second routing line thereby mechanically attaching the first pillar and the second routing line, etching the second metal layer thereby forming the second pillar from an unetched portion of the second metal layer that contacts the second etch mask and the second routing line and exposing a portion of the second routing line that was previously covered by the second metal layer, removing the second etch mask, forming the opening to expose the first pillar and the second routing line and then forming the connection joint on the first pillar and the second routing line.
In a second embodiment, the first pillar and the first routing line are integral with one another, and the second pillar and the second routing line are integral with one another. This is accomplished by providing a first metal layer with first and second opposing surfaces, forming a first recess in the first surface of the first metal layer, electroplating the first routing line on the first surface of the first metal layer and the first pillar in the first recess of the first metal layer, etching the first metal layer thereby exposing portions of the first pillar and the first routing line that were previously covered by the first metal layer, providing a second metal layer with first and second opposing surfaces, forming a second recess in the first surface of the second metal layer, electroplating the second routing line on the first surface of the second metal layer and the second pillar in the second recess of the second metal layer, disposing the dielectric layer between the first pillar and the second routing line thereby mechanically attaching the first pillar and the second routing line, etching the second metal layer thereby exposing portions of the second pillar and the second routing line that were previously covered by the second metal layer, forming the opening to expose the first pillar and the second routing line and then forming the connection joint on the first pillar and the second routing line.
An advantage of the present invention is that the interconnect substrate can contain high density circuitry with short signal lengths. This allows for improved circuit performance, particularly at high speeds and frequencies. Another advantage is that the interconnect substrate can be manufactured using low temperature processes which reduces stress and improves reliability. A further advantage is that the interconnect substrate can be manufactured using well-controlled wet chemical processes which can be easily implemented by circuit board, lead frame and tape manufacturers. Still another advantage is that the interconnect substrate can be manufactured using materials that are compatible with copper chip and lead-free environmental requirements.
These and other objects, features and advantages of the invention will be further described and more readily apparent from a review of the detailed description of the preferred embodiments which follows.